| 摘要 |
PURPOSE:To execute stably and exactly a set, a reset, etc. by holding exactly one of a pair of output lines and the other at a high potential and a low potential, respectively, and utilizing the level of the pair of output lines of a data outputting circuit. CONSTITUTION:The gates of MOS-FETs 13, 14 and same 15, 16 interposed in series between a latch line I/O and I/O', and a node N4 and N5 are connected to a pair of latch lines I/O', I/O and I/O, I/O'. Also, charging transistors 17, 18 are interposed between the pair of latch lines I/O, I/O' and a power source VDD. Moreover, charging transistors 19, 20 are interposed between the nodes N4, N5 and the power source VDD, series connecting points of the MOS-FETs 13, 14 and same 15, 16 and the gate of MOS-FETs 17, 19 and same 18, 20 are connected through a node N6, and N7, to which a clock pulse phi is supplied through a capacitor C1 and C2. Also, at the time of precharge until a row address selecting signal RAS falls and a column address selecting signal CAS falls first, the pair of I/O lines are charged to the power source VDD. |
