发明名称 INTERFACE CIRCUIT
摘要 PURPOSE:To improve checking efficiency on an interface and to transmit/receive correct data by providing a means for sending formal data and its complement data to the sending side as parallel data and a control means for sending the data successively and checking these data on the receiving side. CONSTITUTION:A cut d-type FF1-1 on the sending side latches data signals ID1-ID4 by a signal SET and applies the outputs to a 4-input selector 1-2. The output of a d-type FF1-3 is turned to ''1'' by a signal ST, a binary counter 1-4 is actuated and the inputs of the selector 1-2 are sent to the interface as signals DATA1-DATA4. The signals DATA1-DATA4 are checked by a cut d-type FF3-1, a 4-input comparator 3-2, a d-type FF3-3, and an inverter 3-4 on the receiving side. Thus, the checking efficiency of the data on the interface is improved and correct data transmission/reception is performed.
申请公布号 JPS59208622(A) 申请公布日期 1984.11.27
申请号 JP19830083060 申请日期 1983.05.12
申请人 NIPPON DENKI KK 发明人 KUDOU HIROTSUGU
分类号 H04L29/00;G06F3/00;G06F13/00 主分类号 H04L29/00
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