| 摘要 |
PURPOSE:To obtain an address generating circuit which can be easily produced and used in several divided functions with a small hardware quantity with high regularity, by controlling the address of a data memory. CONSTITUTION:An address control part 3 supplies the base and sizes 19-21 of the addresses read out of a parameter table 2, counter value reading signals 24- 25 of addresses, an instruction code 26, internal states 22-23, a data identification number 12 outputted from an input latch 1, the input data value 13 and an input data type number 14, respectively. Then the address value 27, a read/ write control signal 28 and an effective flag 29 are outputted to an output latch 4; while address counter values 15-16 and internal states 17-18 are outputted to a parameter table memory 2. A data flow processor divides a data memory to use functions for the queuing control of double input data value, the read/ write of the data memory, the generation of a numerical string, the qualification of data value and the transition of the data value, respectively. Then the address of the data memory is controlled.
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