| 摘要 |
PURPOSE:To attain the use of a high speed clock for a digital phase synchronizing circuit by providing respectively an FF circuit between a decoder and a correcting signal generator and between the correcting signal generator and a counter. CONSTITUTION:In considering the critical path (B), a signal counted by a counter 2 is decoded by the (N-2)-th clock at the 1st decoder 3 at first as shown in D, inputted to an FF8 for re-timing, where the signal attains to a waveform delayed by 1-bit as shown in E, thereby eliminating a relative delay nearly to a clock Sc. Further, even if an output signal of the FF8 is inputted to a selecting device 207, the timing is matched again for its output signal F at an FF9 for timing as shown in G and there hardly exists a relative delay to the Sc also in this case. Further, the reason why N-2 is used for the timing of decoding, is that to correct the delay in 2-bit due to the insertion of the FFs 8, 9. |
