发明名称 BUS CONTROL SYSTEM
摘要 PURPOSE:To prevent the breakdown in a bus control system when a specific master unit has a fault by releasing a bus and stopping the control after detecting that the bus using time in a multi-master system exceeds the prescribed value for said multi-master system. CONSTITUTION:In case an access is given mistakenly to an address outside the packaging range of a memory 8, a data fixing signal RDY is not delivered from the memory 8 and a BSY signal line 16 is kept at a low level. If the BSY signal is supplied yet when a prescribed period of time set by a monostable multivibrator within a bus monitor part 19 of a PiD control unit 4 elapses, an ALARM signal is outputted and informed to a main control part 21 via a signal line 23. At the same time, an interruption is applied to another master unit via an iRT4 and a bus 17. Thus the own fault is informed to another master unit. Thus the breakdown in system is prevented.
申请公布号 JPS59202527(A) 申请公布日期 1984.11.16
申请号 JP19830078086 申请日期 1983.05.02
申请人 FUJI DENKI SEIZO KK;FUJI FUAKOMU SEIGIYO KK 发明人 HASHIMOTO CHIKA
分类号 G06F11/30;G06F3/00;G06F11/00;G06F13/00;G06F13/36 主分类号 G06F11/30
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