发明名称 SYNCHRONIZING SYSTEM
摘要 PURPOSE:To prevent the generation of errors of data with a magnetic tape device, etc. having high recording density by obtaining the control voltage which is supplied to a voltage control oscillator of a phase locked loop circuit from mean value of each channel, extracting the variation due to the skew contained in the mean value of each channel to erase it with negative feedback and therefore eliminating the effect of a peak shift to the clock to secure a stable supply of clocks. CONSTITUTION:For the reproduction pulse supplied from an input, the phase difference is detected to the output of a voltage control oscillator 3 by a phase difference detecting circuit 1 of a PLL circuit 4. Then the reproduction pulse is supplied to a mean value detecting circuit 9. The circuit 9 also receives outputs from filters 2 of PLL circuits 4-8 and obtains the control voltage based on the mean value of the driving speed of a magnetic tape to send it to analog sum circuits 17 and 18. The control voltage containing the difference due to the skew is supplied to differential amplifiers 10-13 from filters of the circuits 4-8 and added together by analog sum circuits 14 and 15 respectively. For the oscillator 3 of each PLL circuit, the effect of peak shift is eliminated when the control voltage is applied to the oscillator 3 at an average speed of the magnetic tape. Furthermore the effect of variation of the average driving speed is eliminated with generation of skews. Thus the control is possible with the stable control voltage.
申请公布号 JPS59195310(A) 申请公布日期 1984.11.06
申请号 JP19830069387 申请日期 1983.04.20
申请人 FUJITSU KK 发明人 MATSUURA MICHIO
分类号 G11B20/14 主分类号 G11B20/14
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