发明名称 DATA PROCESSOR
摘要 PURPOSE:To read out the data positioned at both sides of a boundary position for each registration of the data to be given to a buffer memory with just a request given from an instruction unit by reading successively the data covering two blocks out of the buffer memory based on one or two real addresses given from an address converting means. CONSTITUTION:Plural instructions and data are stored in a main memory 10 and a buffer memory 40, and an instruction unit 20 sends the instruction to be executed next to an address control 30. Thus a physical address of 32 bits to be sent to the memory 40 is transmitted onto a line 30A or 30B in response to a logical address. Then the 1st and 2nd banks 42 and 44 send the memory information of 8-byte length onto lines 42A and 44A in response to the physical addresses on the lines 30A and 30B respectively. While the shift amount of a cycle shifter 50 set when an instruction is read out is sent to an align control 90 from the unit 20. This shift amount is stored in a shift byte number register 94, and a signal commanding a corresponding shift action is sent to a cycle shifter 50 from a shift control circuit 95.
申请公布号 JPS59193592(A) 申请公布日期 1984.11.02
申请号 JP19830232349 申请日期 1983.12.09
申请人 HITACHI SEISAKUSHO KK 发明人 KUBO KANJI;WADA KENICHI
分类号 G06F12/08;G06F12/02;G06F12/04 主分类号 G06F12/08
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