发明名称 FLOATING POINT ARITHMETIC UNIT
摘要 PURPOSE:To shorten the time needed for the floating point arithmetic by performing the overflow processing for both the exponent and mantissa parts before the overflow of the mantissa part is produced. CONSTITUTION:An arithmetic circuit 1 performs the arithmetic operations for exponent parts of both floating point data. Then an arithmetic circuit 2 performs an increment operation to the output of the circuit 1. An arithmetic circuit 3 performs the operations for the mantissa parts of both floating point data based on the arithmetic result of the circuit 1. Then a correcting circuit 4 performs an overflow correcting operation to the output of the circuit 3. A multiplexer 5 selects the output of the circuit 1 or 2 based on the arithmetic result of the circuit 3. Then a multiplexer 6 selects the output of the circuit 3 or 4 based on the arithmetic result of the circuit 3 respectively.
申请公布号 JPS6224322(A) 申请公布日期 1987.02.02
申请号 JP19850163352 申请日期 1985.07.23
申请人 NEC CORP 发明人 SUGISHITA KYOSUKE;TANAKA HIDEO
分类号 G06F7/00;G06F7/38;G06F7/483 主分类号 G06F7/00
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