| 摘要 |
PURPOSE:To set independently the output logical low-level voltage with a logical circuit which has a high-speed operation with high yield, by putting an amplitude limiting element between a drain and a power supply in parallel to a load element for a source electrode-coupled FET logical circuit. CONSTITUTION:Load elements 100 and 101 and amplitude limiting elements 103 and 104 are put in parallel between the drains of FET20 and 21 and a power supply. With such a source electrode-coupled FET logical circuit, the voltage gain is decided by the mutual conductance gm between FET20 and 21 and the resistance values of elements 103 and 104. The current flowing to a load element 102 is varied by the input logical high-level voltage (VIH), and the lower limit level of the output logical low-level voltage (VOL) is going to vary. In this case, the voltage VOL can be limited by the elements 100 and 101. Then it is possible to decide the voltage VIH just by the relation between the VIH and VOL, and therefore both FET20 and 21 can be actuated in a saturated area, thereby ensuring a high-speed operation of a logical circuit. |
