发明名称 STORAGE DEVICE UPDATING CIRCUIT OF VITERBI DECODER
摘要 PURPOSE:To reduce the scale of a circuit by applying an address signal indicating an internal state to be updated to an address converter consisting of a cyclic shift register group, and using its output as a retrieval address of a storage device. CONSTITUTION:An initializing signal is applied to a terminal 302 to initialize the storage device 306 and address converter 301. Initial value of cyclic shift registers R0-R2L-1 (L: restraint length of convolution code) of the converter 301 are set to mutually different values. Then, a shift signal is applied to a terminal 303 and the contents of the registers R0-R2L-1 are shifted cyclically. Then when addresses 0-2L<-1> of internal states to be updated are impressed, the contents of the registers show the address of the storage device 306 correspondingly and the contents of the storage device 306 are read out and applied to an update operator 307. The operator 307 operates the amount to be updated at a terminal 308 and the output of the storage device 306 and the updated amount is written in the same address as the read address of the storage device again.
申请公布号 JPS59190751(A) 申请公布日期 1984.10.29
申请号 JP19830064786 申请日期 1983.04.13
申请人 NIPPON DENKI KK 发明人 MURAKAMI SHIYUUJI
分类号 G06F11/10;H03M13/00;H03M13/23;H03M13/41 主分类号 G06F11/10
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