发明名称 INTEGRATION CIRCUIT
摘要 PURPOSE:To perform an integrating operation at a high speed and to deliver an integration signal of high accuracy by giving the integration only to the original input signal after correcting both offset voltage of an integration amplifier and input offset current given from the preceding stage. CONSTITUTION:The input terminal of one side is earthed to an integration circuit, and an integration amplifier 2 connected to an input terminal IN via a resistance 1 is connected to the other input terminal. Then an integration capacitor 3 is connected between the other input terminal of the amplifier 2 and an output terminal OUT of the integration circuit. The 1st switch 4 is connected between the output terminal and the other input terminal of the amplifier 2 together with the 2nd switch 5 connected between the output terminal of the amplifier 2 and the terminal OUT. Furthermore a current limiting resistance 11 is connected between the terminal OUT and the earth. Then a voltage holding circuit consisting of resistances 7 and 10, a capacitor 8 and a buffer amplifier 9 is provided between the output terminal and the input terminal of the other side of the amplifier 2 via the 3rd switch 6. Then the correction is given to the offset voltage of the amplifier 2 and the input offset current supplied from the preceding stage.
申请公布号 JPS59183470(A) 申请公布日期 1984.10.18
申请号 JP19830055005 申请日期 1983.04.01
申请人 HITACHI MEDEIKO:KK 发明人 MORIYA ATSUSHI;MAIO KENJI
分类号 H03M1/52;G06G7/186 主分类号 H03M1/52
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