| 摘要 |
PURPOSE:To prevent malfunction and to decrease the pattern area in circuit integration by producing a two-phase internal clock having a phase different from each other from a basic clock by means of a multiplier circuit or a delay circuit. CONSTITUTION:The basic clock phi is applied to each LSI, i.e., IC1, IC2-ICn via a clock bus BUS1. A data input/output terminal I/O is connected respectively to a BUS2. The basic clock pulse given via the clock bus BUS1 is delayed by the delay circuit D of each clock producing section, a delay signal phid is obtained and the two-phase internal clocks phi1, phi2 without mutual duplication are obtained by logical products AND11 and AND12 of positive logic and negative logic for the basic clock phi and the delay signal phid, thereby simplifying the internal constitution of the LSIs, and the pattern area is reduced also, and the circuit is operated stably and surely even if plural LSIs are operated especially in the way of interlocking. |
