发明名称 ERROR CORRECTING AND DECODING SYSTEM
摘要 PURPOSE:To perform correction and decoding until a prescribed threshold value is obtained by adding a subtraction circuit to a majority decision circuit so as to set a threshold value to be decided of the majority decision circuit to a specific value within the number of the input devices of the majority decision circuit and subtracting this threshold value to be decided via the subtraction circuit after cyclic correction. CONSTITUTION:A CPU sets a threshold value designating signal 129 to ''17''. Then, the CPU generates a start signal 110 to reset 124 a syndrome register 106. Further, the CPU loads sequentially 1-packet 272-bit information by 16-bit each in 17 divisions. the loaded data is superimposed on a data 114 before error correction to generate a load instruction 111. A load gate signal 120 is generated based on this signal 111 to attain data loading before error correction and 16-bit shift to registers 103 and 106. When this procedure is repeated 17 times, the generated syndrome is stored in the register 106. Then, the correcting operation is commanded by the CPU. After the error correction of 16-bit is performed by a correcting signal 113, the CPU reads a data 115.
申请公布号 JPS59181841(A) 申请公布日期 1984.10.16
申请号 JP19830054002 申请日期 1983.03.31
申请人 NIPPON HOSO KYOKAI 发明人 YAMADA TSUKASA
分类号 H03M13/00;H03M13/43 主分类号 H03M13/00
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