发明名称 BUFFER MEMORY CONTROLLING SYSTEM
摘要 PURPOSE:To enable simultaneous processing without keeping swap out operation, block load operation and without making succeeding request that can be processed in a buffer memory wait by interleaving the buffer memory and enabling plural pocessing. CONSTITUTION:A data array is interleaved to make it two-ways; bank A 243, bank B 244. Write data selection circuits 252, 251, write address selection circuits 252, 253, read data and read write block selection circuit 256, 257 of each data array are duplicated respectively. The data array 241 selects the bank A 243 and bank B 244 by the lowermost bit of request address as shown in the figure. In this constitution, the bank A 243 and bank B 244 is accessed depending on whether the lowermost bit of request address is 0 or 1, i.e. whether the request address is odd number or even number. Simultaneous accessing is made possible if the value of lowermost bit is different.
申请公布号 JPS59177782(A) 申请公布日期 1984.10.08
申请号 JP19830050855 申请日期 1983.03.25
申请人 NIPPON DENKI KK 发明人 HARA TADASHI
分类号 G06F5/16;G06F12/08 主分类号 G06F5/16
代理机构 代理人
主权项
地址