| 摘要 |
In a data processing system in which two or more asynchronous processors operating as masters interchange requests and responses with a control unit that in turn controls a number of peripheral devices and operates as a slave to the processors, repetitive requests from a high speed processor can give rise to an impasse condition in which the control unit is blocked from completing the previously initiated sequence between a peripheral device and another processor. In accordance with the invention, the interface between the processors and the peripheral devices incorporates means which detect an uninterrupted sequence, of predetermined length, of busy responses from the control unit. If such responses are not interrupted by other actions, the system temporarily exercises independent control, returning a busy signal to the processors while enabling the control unit to ascertain whether reconnection to a specific processor is needed as the next step in a previously initiated processor program. If so, the control unit is enabled within the predetermined interval to effect the reconnection, either within the allotted time or on a succeeding repetition of the cycle. The exercise of a limited initiative for a predetermined time interval does not alter the basic master-slave relationship or unduly delay data transfer operations. |
