| 摘要 |
A decorder circuit which receives a plurality of address signals and selects one of the n x m word lines for driving a semiconductor memory device. The decoder circuit includes a high level selection circuit which receives the upper address signals and produces n outputs, one of the n outputs is selected to be a high level, while the other (n-1) outputs are rendered at a low level. The decoder circuit also includes a low level selection circuit which receives the lower address signals and produces m outputs, one of the m outputs is selected to be the low level, while the other (m-1) outputs are rendered at the high level.
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