| 摘要 |
<p>PURPOSE:To attain the setting of an optimum value in response to the applied system of circuit integration by making the value of the number of stages to be protected variable and designating it by a binary number externally at the operation. CONSTITUTION:An AND gate 3 outputs a dissidence pulse when a clock pulse is discriminated as inverted phase, and the dissidence pulse is counted by an n-stage of counters 4. Further, as AND gate 5 outputs a coincidence pulse when it discriminates the clock pulse an in-phase, and the coincidence pulse resets the counters 4 through an OR gate 6. Contents of the counter 4 and the number of stages to be protected inputted by a binary number from a protecting number of stage designating input terminal 7 are compared with an EX-NOR gate 8, and when they are coincident, an output of an AND gate 9 goes to 1. This output is led to a control pulse output terminal 10 so as to invert the phase of the clock pulse and to reset the counter 4 via a delay circuit 11 and a gate 6.</p> |
