发明名称 METHOD FOR TESTING SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PURPOSE:To increase the efficiency of measurement of the titled integrated circuit by a method wherein a plurality of probing needles, which can be selectively moved in vertical direction, are provided on a substrate in matrix form, said substrate is placed on the semiconductor wafer whereon a plurality of ICs are formed, and electric characteristics are tested by moving the desired probe needle using a control system and have the probe needle to come in contact with the IC chip. CONSTITUTION:The lower substrate 2-1, whereon a number of probe needles 3 which can be telescopically moved facing downward are provided in matrix form, is placed on the semiconductor wafer 1 whose electric characteristics are going to be tested. Then, the upper substrate 2-2 having a number of vertically movable press pins 4, to be used to push out the desired probe 3, is provided on the lower substrate 2-1, and the probe 3 is pushed out and brought to come in contact with the measuring point of the wafer 1 using a probe needle driving control system 5 through the intermediary of an air cylinder 7 and a pipe 8. Subsequently, the electric characteristics of the measuring point is measured using the measuring system 6 which is connected to the substrate 2-1.
申请公布号 JPS59171131(A) 申请公布日期 1984.09.27
申请号 JP19830005095 申请日期 1983.01.13
申请人 FUJITSU KK 发明人 TOGASHI KENJI
分类号 H01L21/66;(IPC1-7):H01L21/66 主分类号 H01L21/66
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