| 摘要 |
PURPOSE:To simplify the design and to stabilize the operation of a bit error detecting circuit by discriminating the value of the 1st bit after resetting an arithmetic register during calculation of the 1st bit and then deciding the input of the arithmetic register from the 1st bit value when the 2nd bit is calculated. CONSTITUTION:When a bit error is checked for a data train, the 1st bit A of the reception data 20 is extracted through an AND gate 74 and then delayed by a D flip-flop 75 at the time position of the 2nd bit of the data 20. In this case, the outputs 76 and 77 of the flip-flop 75 are shown by the solid lines and broken lines when the bit A is set at 1 and 0 respectively. Therefore the outputs 82 and 83 of a D flip-flop 17 are selected by AND gates 79-81 when the bit A is set at 1 and 0 respectively for a D input 78 of the flip-flop 17 obtained immediately before calculation of the 2nd bit B. The output 83 of the flip-flop 17 is selected at time positions of bits excepting the bit B. |
