发明名称 |
Power divider/combiner circuit as for use in a switching matrix |
摘要 |
A one port-to-M port passive signal power divider circuit (or combiner circuit) where M>2 and NOTEQUAL 2N, M and N are integers, includes M - 1 two-way in-phase passive power dividers having a signal delay D through each path in one or more delay devices having delay D. Each output of each two-way power divider is coupled to an input of another power divider, a delay line or an output port, the arrangement being such that the delay through all ports of the power divider are equal. In accordance with a further embodiment of the invention the outputs of a passive power divider are connected to two-way switches using active components. The switches under control of a control circuit are utilized to switch the input signal to the power divider to any one of 2xM output terminals of the switches.
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申请公布号 |
US4472691(A) |
申请公布日期 |
1984.09.18 |
申请号 |
US19820383960 |
申请日期 |
1982.06.01 |
申请人 |
RCA CORPORATION |
发明人 |
KUMAR, MAHESH;UPADHYAYULA, LAKSHMINARASIMHA C. |
分类号 |
H01P1/15;H01P5/12;(IPC1-7):H01P1/10 |
主分类号 |
H01P1/15 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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