| 摘要 |
PURPOSE:To generate a clock with constant pulse width by constituting a slave side FF section of two FFs by two sets of FF circuits outputting inverse polarities with each other and combining generated pulses having different phase. CONSTITUTION:Since the polarity of a clock input to an MS E.EF44-1 and an MS E.EF44-2 is inverted by a gate 34 with each other, the FF44-1 and the FF44- 2 are operated with a shift of a half cycle. For example, phi1-phi3 having a prescribed pulse width with a delay of 4DELTATG in leading and a delay of 3DELTATG in trailing are formed. The phi0 ANDs and output Q01 of the FF41-1 delayed by 4DELTATG in leading and an output Q00 of the FF44-2 delayed by 3DELTATG in trailing, the phi1 ANDs an output Q01 of the FF44-2 delayed by 4DELTATG in leading and an output Q10 of the FF44-1 by 2DELTATG in trailing, and the phi2 and phi3 are formed similarly, allowing to produce the clocks with a prescribed pulse width. |
