发明名称 ARITHMETIC DEVICE
摘要 <p>PURPOSE:To attain quickly the operation by applying four numerical outputs of the 1st and 2nd input numerical data producing circuits to two registers via a multiplication circuit and a substraction circuit and outputting a signal having a proper code. CONSTITUTION:Input numerical information given to input terminals 1, 2 and 3, 4 is inputted respectively to input numerical value data producing circuits DPa, DPb and the outputs are fed to a multiplication circuit MPY as the content of constitution shown in Figs. (a) and (b). A signal having the constitution as shown in Fig. (c) is outputted from the circuit MPY. Signals K2, K4 from the LSB to the digit A are given by the signal as minuends to a subtraction circuit SUB and signals K1, K3 from the 2A digit to the MSB are given as minuend signals. Further, a signal [(K1.K4)+(K2.K3)] is fed to a register RSTa from the circuit MPY and a signal [(K2.K4)-(K1.K3)] is given to a register RSTb from the circuit SUB and the signals are outputted from the both registers with a proper code.</p>
申请公布号 JPS59158472(A) 申请公布日期 1984.09.07
申请号 JP19830033158 申请日期 1983.03.01
申请人 NIPPON VICTOR KK 发明人 TANAKA YOSHIAKI
分类号 G06F17/14;(IPC1-7):G06F15/332 主分类号 G06F17/14
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