发明名称 DATA TRANSFER SYSTEM OF MULTIPLE ADDRESS COMMUNICATION
摘要 PURPOSE:To prevent data omission and double reception of data by receiving only a frame of multiple address communication for securing a receiving buffer after a specific frame is received unconditionally, and inhibiting the reception of multiple address communication after the reception of multiple address communication. CONSTITUTION:When a frame addressed to all stations is to be transmitted from a data transmitter 4 to respective data transmitters, the processor in the data transmitter 4 transmits a command frame for setting busy flip-flops 123 and transmission inhibition flip-flops 124 in respective data transmitters firstly to all the stations. For example, multiple address communication addresses to all the stations is sent again to the data transmitter 4 of the transmitting station because of the busy buffer stations of other data transmitters after the busy flip- flops 123 are reset. In this case, a frame detecting circuit 101 sends signals to signals 202, 203, and 204, but flip-flops 123 and 130 are off, so a signal is generated at the output of an exclusive EOR circuit 405 and a signal is generated on neither a receivable signal line 303 or 304, so that a frame receiving circuit 102 is not actuated.
申请公布号 JPS59158155(A) 申请公布日期 1984.09.07
申请号 JP19830032292 申请日期 1983.02.28
申请人 NIPPON DENKI KK 发明人 YASUE KAZUO
分类号 H04L12/18 主分类号 H04L12/18
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