Error detection circuitry for digital systems.

摘要

Circuitry for detecting errors in a digital bit stream comprising a succession of data blocks and wherein each block incorporates a parity check (P). At an error monitoring location (e.g. 100), a bistable device (e.g. 103) toggles in response to either a logical <<1>> or <<0>> in the bit stream. The output of the bistable device is sampled at a submultiple of the bit rate and compared with a predetermined criterion to detect bit errors.