| 摘要 |
PURPOSE:To debug a program having a hierachical module structure efficiently by detecting call and return instructions to be executed by a CPU on the master machine side, counting up/down the instructions and stopping/starting the operation of the CPU at an optional point. CONSTITUTION:A decoder 5 detects the call/return instructions, turns a signal SC/SR to ''1'' and then turns the output of a gate G2/G3 to ''1'' together with the operation of a timing signal F1. A counter 11 counts up or down U/D the output of the gate G2/G3. A decoder 12 decodes the calculated value of the counter 11, and when the counted value reaches the initial value (0), a signal A0 is turned to ''1''. At that time, a gate G1 generates an output by the return instruction, and when the FF7 is set up, the AND gate G3 outputs ''1'', an FF6 is set up through a gate G4, and a stop signal BK is outputted to stop the CPU1. If the return instruction is detected when the counter indicates the initial value, the operation of the CPU on the master machine side is stopped and the complexity finding out a return point from a slave module to a master module is removed. |
