| 摘要 |
PURPOSE:To attain the error detection of the mBIC code rule without synchronism by ORing exclusively an input signal and a signal delaying the said input signal by a 1-bit delay circuit. CONSTITUTION:A (0) level holding circuit 8 is a circuit keeping to output (0) until a reset signal is inputted when an output of an AND circuit 7 is (0). The output of the circuit 8 is logical (1) when an input to supervisory circuits 4-1-4 is always logical (1), and the output goes to (0) until a reset signal is inputted when (0) is inputted once. Since an output of the EX-OR between a c-bit and a bit just before the c-bit is always logical (1) normally, a bit output of a shift register 3 corresponding to the c-bit goes to (1). The probability of (1) and (0) for the EX-OR of other bits is 1/2 and the probability where the output of the supervisory circuit is logical (1) closes to (0) when the period is increased. Thus, the error is detected by supervising the output of the supervisory circuit. |
