发明名称 MULTIPORT MEMORY ARRAY
摘要 <p>MULTIPORT MEMORY ARRAY Dual port capability in a memory array is achieved by an arrangement of the memory cells such that for each cycle of the memory operation two accesses may be performed. This result is achieved by taking advantage of the bit line precharging interval. A second bit line accessing pair is added to each memory element, and each cycle is split so that when one bit line is in the accessing mode, the other bit line is in the precharging mode. The speed of the memory is effectively doubled by using this technique.</p>
申请公布号 CA1173566(A) 申请公布日期 1984.08.28
申请号 CA19820400614 申请日期 1982.04.07
申请人 WESTERN ELECTRIC COMPANY, INCORPORATED 发明人 MOFFITT, BRYAN S.;ROSS, ALEXANDER R.
分类号 G11C11/41;G11C8/16;(IPC1-7):G11C8/02;G06F13/06 主分类号 G11C11/41
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