| 摘要 |
A memory system (11) for a computer detect data errors, address errors and operation errors to increase the reliability of data stored in the memory system. Address errors are detected by encoding address parity information into the data check field of each memory location. A signal is generated in each memory module (21) indicating the status of operations of that memory module and is transmitted to the processor subsystem (13, 15, 17 & 37) of the computer for comparison with a signal indicating the status of operations of the processor subsystem to ensure that all memory modules (21) and the memory control in the processor are receiving the same commands. |
