| 摘要 |
Disclosed is a memory system for reading and writing variable length data fields. Each of the data fields are addressed by the combination of a word address, a bit address, and a field length. Internal to the memory system, a total of 2N cells are addressed by each word address where N is the maximum field length. But only a portion of the addressed cells are selectively enabled in response to the bit address and field length. An N bit shifter right justifies the output data from the selectively enabled cells, and also realigns right justified input data to be written into the selectively enabled cells.
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