发明名称 CONTROL DEVICE OF ADDRESS
摘要 PURPOSE:To perform the resource utilization and processing of a computer system efficiently by setting up the change of a common area and a switching enabled area in a memory segment optionally. CONSTITUTION:When a memory address is outputted from an operation processor through an address bus 14, a comparator 12 compares the contents of the address bus 14 with the contents of a border register 11. When the contents of an address bus are smaller than that of the border register, the output line of the comparator 12 is turned on and a gate 13 transmits the contents of a segment register 10 to a segment bus 15. Consequently, the memory segment selected by the segment bus 15 is disabled to be accessed. If the contents of the address bus is larger than that of the border register, the output line 15 of the comparator 12 is turned off and the gate sends all the bits ''0'' to the segment bus without sending the contents of the segment register 10, so that the memory segment ''0'' is selected. The value of the border register 11 can be optionally set up by a program.
申请公布号 JPS59144965(A) 申请公布日期 1984.08.20
申请号 JP19830018129 申请日期 1983.02.08
申请人 CANON KK 发明人 KAWABATA YOUICHI
分类号 G06F12/06;G06F13/00 主分类号 G06F12/06
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