| 摘要 |
PURPOSE:To process discontinuous data at a high speed by rearranging the data stored in the addresses of a fixed array by means of hardware. CONSTITUTION:A DMA controller 31 checks whether a transfer request signal TXPEQ exists for each fall of a CPU cycle clock CLK2. When the signal TXPEQ exists, the addresses are counted up or down and transmitted. A TXREQ producing part 33 of a transfer request signal producing circuit 30 synthesizes a transfer request to the controller 31 through circuits 34-36. A 3- address count-up TXREQ producing circuit 34 produces a TXREQ to advance the three addresses within a latching cycle during which a data latch circuit 39 latches the data given from an RAM32 through a data bus. While a 1-address count-up TXREQ producing circuit 35 produces a TXREQ to advance an address within said latching cycle. A DMA starting circuit 36 starts the DMA with software. |
