| 摘要 |
PURPOSE:To display accurately a half tone by dividing the PCM signal of (n) bits into high-order and low-order parts and giving the PWM conversion to the high-order and low-order bits by the front edge and rear edge modulation systems respectively on the basis of the same time point of division. CONSTITUTION:A shift register 10 stores the PCM signals supplied from a data signal input terminal 11 in the form ofthe picture data and then converts the serial input data into the parallel data for output. This output is divided into low-order 2 bits and high-order 2 bits and connected to input sides 16 and 17 at one side of a magnitude comparator 15 of 2 bits via a selector which selects high-order or low-order 2 bits out of 4 bits via latch circuits 12 and 13. An input terminal 18 for clock signal is connected to a binary counter 19 of 4 bits. The upper bits of the counter 19 are connected directly to a selector 22; while the lower bits are connected to the selector 22 via inverters 20 and 21. These bits are connected to input sides 23 and 24 at the other side of the comparator 15. |
