发明名称 BY-PASS CONTROL SYSTEM OF ARITHMETIC DEVICE
摘要 PURPOSE:To improve a by-pass control circuit and to simplify the hardware by by-passing only the positive/negative sign of an arithmetic result to an operand register when the arithmtic result of a leading instruction is transferred to a data register. CONSTITUTION:A multiplexer 13 is coupled with only the positive/negative sign part 12 of an A register 2. The output line of a floating register FR1 and the by-pass line from an E bus are coupled with both circuits 13 and 14, and the by-pass line from a D bus is not coupled with the circuit 14. Consequently, only the positive/negative sign of the arithmetic result outputted from the 1st arithmetic part 4 to the D bus is by-passed to the register 12. Then, an address comparing circuit 15 checks whether the leading (n) of the arithmetic result of the leading instruction coincides with the storge location N or M of the 1st or 2nd operand of the trailing instruction and performs by-pass control when n=N or when n=M. Consequently, the by-pass control circuit is improved and the hardware is also simplified.
申请公布号 JPS59123937(A) 申请公布日期 1984.07.17
申请号 JP19820231890 申请日期 1982.12.29
申请人 FUJITSU KK 发明人 SUGIURA SATOSHI
分类号 G06F7/00;G06F9/38 主分类号 G06F7/00
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