发明名称 SYSTEM FOR DETECTING FAILURE
摘要 PURPOSE:To detect automatically a failure of a register by the firmware or hardware without requiring the operator by comparing a data stored in the register and the inversion of each bit of the data. CONSTITUTION:A transferred data is inputted from a terminal A of a multiplexer 20 and fed to registers 1, 6 and 11 and one of the data in the registers is selected by an output of AND circuits 2, 7 and 12. Suppose that the register 1 is selected, after the data is stored in the register 1, it is read and when an error is detected by a parity error detecting circuit 5, an error signal is transmitted to OR circuits 3, 17. The signal through the OR circuit 3 is fed to the circuit 2, which makes the register 1 enable, and the signal fed to the circuit 17 makes a register 22 enable via an AND circuit 19. Further, the data from the register 1 is stored in the register 22 via a multiplexer 16. Moreover, each bit of the data is inverted by an NOT circuit 21, the result enters the register 1 by switching operation of the multiplexer 20, and the inverted data enters a comparison circuit 23 via the multiplexer 16 and compared.
申请公布号 JPS59121552(A) 申请公布日期 1984.07.13
申请号 JP19820230611 申请日期 1982.12.28
申请人 FUJITSU KK 发明人 EITAI YOSHIHIRO;KADOI IZUMI
分类号 G06F11/10;G06F11/00;G06F11/07 主分类号 G06F11/10
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