| 摘要 |
PURPOSE:To increase easily a display data by switching the address of an RAM to designate an address area which is different from that which a CPU and a channel access at a usual time when a reset signal is outputted to the RAM from the CPU. CONSTITUTION:When writing a state data in the RAM21, an address is given to the RAM21 through OR gates 23, 24 from a control circuit 22 to open a gate 25 and to provide the data to a data signal line 26. In this case, the output of the gate 24 is a ''1'' bit, and for instance, it is always set to ''0''. On the other hand, the CPU reads out the state data in the RAM21 to outpt to an address signal line 27, to send a signal to the RAM21 from the OR gate 23, and read also the state data by opening the gate 28. In this case, the output of the OR gate is ''0'', and the CPU does not output an address as for this ''1'' bit. Also, an FF29 is used as a switching device to provide the output of its Q terminal to the gate 24, and the output of an inversion Q terminal to the control circuit 22. |
