| 摘要 |
PURPOSE:To avoid consecutive ''0s'' in the combination of 3-bit information by applying block conversion for the conversion from 2-bit into 3-bit. CONSTITUTION:The information applied to an input terminal 1 is transferred in a shift register 2 by 2-bit each and 5-bit information is supplied to a convertion logic 3. Further, the 3rd bit of the information converted prior to a shift register 4 is supplied to a conversion logic 3. Then, the conversion according to the conversion formula is attained by the conversion logic 3 and the converted 3-bit information is supplied to the shift register 4. Moreover, a clock signal having a frequency 3/2 times that of the input signal is supplied to the shift register 4 from a clock terminal 5, and 3 bits are read sequentially. This signal is applied to a JKFF 6, and an NRZI-modulated signal is extracted to an output terminal 7 by the clock signal from a terminal 5. |
