Package for enclosing semiconductor elements

摘要

A package for enclosing semiconductor elements having side surfaces at which cross sections of conductive wires for receiving a voltage to effect electric plating are exposed. The side surfaces are provided with a static electricity-preventing device, such recesses formed in the side surfaces, insulating films formed on the side surfaces or removable frames positioned on the side surfaces, so that a high voltage due to static electricity from an exterior source is not applied to the conductive wires.