| 摘要 |
PURPOSE:To obtain a linear circuit and an I<2>L circuit having a high speed signal transmission characteristic by providing additionally an inverse operating transistor (TR) so as to prevent the deep saturation of the TR connected to the I<2>L circuit. CONSTITUTION:The interface circuit comprising the 1st TRQ1 of forward operation controlled for conduction with an output signal of the linear circuit 11 and the 2nd TR of inverse operation whose collector is connected to the input stage of the I<2>L circuit, whose emitter is grounded and whose base is connected to the collector of the 1st TRQ1, is provided with the 3rd TRQ3 of reverse operation whose base and collector are connected to the collector of the 1st TRQ1 and whose emitter is grounded. In this case, the collector area ratio of the 2nd and the 3rd TRQ2, Q3 is set to a value where the 2nd TRQ2 does not reach a deep saturated state. Thus, a high speed signal transmission characteristic is provided. |
