| 摘要 |
PURPOSE:To eliminate the need for high-speed processing for conversion into signals having different sampling frequencies by providing a coefficient control means which produces an output after selecting the coefficient of a digital filter and then multiplying this coefficient by the output of a data series speed converting means and an arithmetic means which produces an output with addition of the result of said multiplication. CONSTITUTION:Flip-flops (FF) D-1-D-5 and D-6-D-10 are set opposite to a data series speed converting part 11. Multipliers 21-1-21-5 are set opposite to a coefficient control part 12, and an adder 22 is set opposite to an arithmetic part 13 respectively. The input data are successively read into FFs D-1-D-5 by an f1 clock, and the output data of the FFs D-1-D-5 are read in parallel to FFs D6-1-D-10 by an f2 clock. The output data FFs D-6-D-10 are multiplied by the coefficient through multipliers 21-1-21-5 in response to the control signal. The outputs of the multipliers 21-1-21-5 are added together by the adder 22. Thus the output data subjected to a desired frequency conversion is obtained as a result of addition. |
