发明名称 MULTIPROCESSOR SYSTEM
摘要 PURPOSE:To realize a meahs which makes the load applied to each processor uniform without pressing upon the throughput of the processor, by processing jobs belonging to a job queue in accordance with a prescribed order. CONSTITUTION:A read indicating circuit 16 transmits job read requests to a job reading circuit 70 at intervals of a prescribed period. The circuit 70 scans a read allowable memory 15 to detect a job queue JSx set to logical value (0). A read address JPx corresponding to the job queue JSx is extracted by a job read pointer in a job receiving part 4, and a job Jxj corresponding to this address is extracted from a job buffer 5. This job is distributed to a processor 1 or 2, and a corresponding read allowable bit of the job queue JSx in a memory 15 is updated to (1), and the processor 1 or 2 of the distribution destination is recorded in accordance with the job queue JSx. Consequently, when the circuit 70 which receives next the read request from the circuit 16 refers to the memory 15, the job Jxj is not extracted from the job queue JSx whose allowable bit is set to (1).
申请公布号 JPS59106064(A) 申请公布日期 1984.06.19
申请号 JP19820216421 申请日期 1982.12.10
申请人 FUJITSU KK 发明人 SUZUKI TAKASHI;INAMI TAKASHI;SUGAWARA SUBEO
分类号 G06F15/16;G06F15/177 主分类号 G06F15/16
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