| 摘要 |
PURPOSE:To offer a compact and inexpensive memory circuit by using plural inexpensive dynamic RAMs with large capacity and medium speed. CONSTITUTION:The 1st data is transmitted to a picture memory circuit together with a latch pulse. Address data A1, A0 are inputted to a decoder 22 from an address counter 24, and on the other hand, an output of the decoder 22 by the input of latch pulse is transmitted to address latch registers 26-1 and 28-1 as a clock input CP, the address and data for D-RAM 20-1 are outputted from each register and the write operation to a D-RAM 20-1 is started. A counter 24 is incremented while the next latch pulse comes. When the 2nd and succeeding data and latch pulse are incoming, the write is continued sequentially cyclicly to each RAM 20-2 similarly. Further, each RAM is finished for the preceding cycle until the next cycle comes. |
