| 摘要 |
PURPOSE:To speed up an operating clock by providing set circuit capable of setting or resetting the M-th stage and resetting or setting the N-th stage in setting the number of stages of the N-stage of a ring counter to a value M(<N). CONSTITUTION:When the ring counter circuit comprising FF1-FFN-1 is desired to be set to the M-stage and an FFM is set by an output of a set circuit 30 by using a number of stage set signal, the output Q of the FFM goes to level 1, the output Q of the FFM-FFN-1 goes always to level 1 at the operation. Thus, only when all the outputs Q of the FF1-FFM-1 are at level 1, the output Q of the FF1 is set to 0 level by the next clock with an output of an NAND gate 10. When it is desired to be initialized from the K(<M)-stage, an FFK is reset from the circuit 30 by a reset signal, and when the output Q is brought into 0 level, the output Q of the FF1 is set to a phase being 0 level after the clock of the (M-K)-set after the release of reset. |
