发明名称 CONFIRMING SYSTEM OF EXECUTION SPEED OF SEQUENCE CONTROLLER
摘要 PURPOSE:To make an optimal system design possible by reading out instructions of contents of a program, which is stored in a program memory successively in the processing order and integrating processing speeds of respective instructions. CONSTITUTION:The execution speed of each instruction is stored in a system program memory 11, and a program loader 5 reads out instructions, which are stored in a user program memory 3, successively by the operation of an execution speed confirming key provided on a keyboard 14 and retrieves execution speed of respective instructions from stored contents and adds them to an execution speed integral counter. When an END instruction is read out and its execution speed is added to the integral counter, the read of instructions is terminated. Thus, in case that a relay circuit is substituted with a sequence control circuit, an optimal deisgn which takes the processing speed into consideration and recognizes the use limit is possible.
申请公布号 JPS5998212(A) 申请公布日期 1984.06.06
申请号 JP19820207387 申请日期 1982.11.26
申请人 FUJI DENKI SEIZO KK 发明人 KIKUCHI HIROSHI;SHINPO TOKUTAROU;KOIZUMI KOUJI;FUJITA KAZUHIRO;HISHINUMA MASAKATSU
分类号 G06F11/34;G05B19/048;G05B19/05;G05B23/02 主分类号 G06F11/34
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