| 摘要 |
For A/D conversion of an analog signal, a PDM signal is produced from said analog signal by natural sampling, and the duration of each PDM pulse is counted by means of a pulsed, freewheeling binary counter (7). In the digital signal thus obtained, the rectangular-wave form clock signal is used as the least-significant binary signal for the binary counter. The start of sampling and hence of counting is in each case initiated using the most-significant binary signal. For simultaneous D/A conversion of a digital signal in a common circuit arrangement, the digital signal is continuously compared with the binary output signal of the same binary counter, by means of a digital comparator (25). A new comparison is initiated in each case by the most-significant binary signal of the counter output. The output signal of the comparator (25) is a PDM signal which is converted by means of a low-pass filter (55) into the desired analog signal. A clock signal which is non-linear with time is applied to the binary counter (7) in order to compand the digital signal. <IMAGE> |
