| 摘要 |
PURPOSE:To shorten a bus occupation time, by securing always corresponding data in a buffer memory to prepare for a series of direct memory access to be transferred from the same input/output controller. CONSTITUTION:Buffer memories 20, 21-2n including control bits indicating the availability are provided, and a direct memory access DMA start address which the input/output controller requests is used to execute the memory load for a main storage device instead of the input/output controller. If an idle area is generated in memories 20-2n, the memory load is executed with continuous addresses consecutively, and corresponding data is always secured in buffer memories to prepare for a series of DMA to be transferred from the same input/output controller. Thus, the conversion from the split cycle to the interlock cycle is provided also, and the DMA transfer is realized in a high-speed access time. |
