| 摘要 |
PURPOSE:To correct error due to many defects with small quantity of hardware and redundancy by using a parity bit added to each row and column of a bit array and a defect indication flag. CONSTITUTION:A memory device 1 selects and access one bit or plural bits from some memory blocks 2 to output the data bits 3 of (M+1)X(N+1) bits that forms a bit array of (M+1) rows and (N+1) columns. At the same time, the memory device 1 outputs the defect indication flag of (M+1)X(N+1) bits that corresponds one to one to each data bit 3. The device consists of (M+1)X(N+1) data latches 5 and flag latches 6 arrayed in (M+1) rows and (N+1) columns, (M+1) second correction circuit 7 that performs row correction provided in each row, (N+1) first correction circuit 8 that performs column correction provided in each column, and a change-over circuit 200 that actuates the second correction circuit 7 and the first correction circuit 8 alternately for access. |
