发明名称 SYNCHRONIZATION SEPARATING CIRCUIT OF DIGITAL SIGNAL
摘要 PURPOSE:To protect dropout and to prevent malfunction by feeding back an output of a counter controlled by a synchronizing pattern to an input side and deciding the phase of the synchronizing pattern by a jitter compensation window generator operated by said output. CONSTITUTION:When a serial digital signal is inputted to a terminal T1, a synchronizing pattern detecting gate 2 detects the synchronizing pattern via a serial/parallel converter 1. A counter 3A is controlled by the synchronizing pattern, the output is fed back to the input side of the counter and inputted to the jitter compensating window generator 9. Since no output is obtained if the next synchronizing pattern is not fed to the window generated after about 1 frame from the synchronizing pattern at the jitter compensation window generator 9, no output is obtained even if the same pattern as the synchronizing pattern is generated intermediately. Since the output of the counter is fed back, the output is reset at each frame and the dropout is protected.
申请公布号 JPS5985154(A) 申请公布日期 1984.05.17
申请号 JP19820194885 申请日期 1982.11.05
申请人 AKAI DENKI KK 发明人 SAITOU OSAMU
分类号 H04L7/08;H04L7/04 主分类号 H04L7/08
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