| 摘要 |
PURPOSE:To ensure smoothing processing with high efficiency by counting clock signals by an auxiliary counter from a time point when the digital data is preset to a counter to a detecting time point of a comparator and obtaining the digital data of desired size and order. CONSTITUTION:The digital data are selected through a processing window and stored in registers 12a and 12b-12n and then preset to up-counters 13a and 13b-13n respectively to be advanced by a clock signal CK. The output of the up-counter sets FF15a and 15b-15n, and the numbers of set outputs are added 16 together and applied to a comparator 17 to be compared with the prescribed set value fed from an input port 18. When the number of carry signal outputs reaches said set value, the comparator 17 supplied a counting stop signal to a down-counter 19 as an auxiliary counter. Then the digital data obtained by the counter 19 are delivered through an output port 20 in the form of the data selected in the desired order. |
