Stored program digital data processor

摘要

A store had addressable locations in two portions RAM A and RAM B. An instruction highway enables locations to be addressed independently in RAM A and RAM B. An adder adds the contents of two addressed locations in RAM A and RAM B respectively. A register receives the sum from the adder and also interrupt signals. A connection enables the contents of part of the register to be written back in RAM A and a further connection enables the contents of part of the register to be written back in RAM B. Control is by a program counter and instruction ROM which provides instructions on the highway, shift pulses for the register and a latch enable signal for enabling a latch to store an output word from the highway. One register bit and a bit from the instruction ROM control presetting of the program counter to a jump address.