发明名称 POWER-ON CLEAR CIRCUIT
摘要 <p>PURPOSE:To stabilize an operation by controlling an operation of charge and discharge of a delaying circuit by an output after an electric power source of a circuit to be cleared is turned on. CONSTITUTION:After an electric power source is turned on, when power supply voltage rises gradually and becomes the power supply voltage by which a logic 3 can be operated, its output becomes a high or low level. In case when the output 4 is in a low level, an operation of charge and discharge of a delaying circuit 1 is advanced by a controlling circuit 5. In case when the output 4 is in a high level, the charge and discharge of the delaying circuit 1 are inhibited by the controlling circuit 5. Thereafter, as the power supply voltage rises, an output 2 of the delaying circuit 1 rises, and when the logic 3 is reset, the output 4 is changed to a low level, and the charge and discharge of the delaying circuit 1 are executed.</p>
申请公布号 JPS5975329(A) 申请公布日期 1984.04.28
申请号 JP19820187197 申请日期 1982.10.25
申请人 SEIKO DENSHI KOGYO KK 发明人 TANAKA KAZUYUKI
分类号 G05F1/56;G06F1/24;H03K17/22 主分类号 G05F1/56
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